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May 1977 (vol. 26 no. 5)
pp. 474-479
F.P. Preparata, Coordinated Science Laboratory and Department of Electrical Engineering, University of Illinois
In this paper we presentt family of techniques for the design of combinational networks whose objective is the reduction of the number of levels, subject to a constraint on the fan-in of the logic gates. We show that a Boolean expression with n literals and involving the connectivest AND and OR can be restructured so that the resulting network of AND and OR gates has depth at most Cllog
Index Terms:
Boolean, expressions, combinational networks, computational complexity, design algrithms, fan-in, network depth, number of levels, parallel computation.
Citation:
F.P. Preparata, D.E. Mulller, A.B. Barak, "Reduction of Depth of Boolean Networks with a Fan-In Constraint," IEEE Transactions on Computers, vol. 26, no. 5, pp. 474-479, May 1977, doi:10.1109/TC.1977.1674864
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