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May 1977 (vol. 26 no. 5)
pp. 458-473
M.C., III Pease, Information Science Laboratory of the. Information Science and Engineering Division, Stanford Research Institute
This paper explores the possibility of using a large-scale array of microprocessors as a computational facility for the execution of massive numerical computations with a high degree of parallelism. By microprocessor we mean a processor realized on one or a few semiconductor chips that include arithmetic and logical facilities and some memory. The current state of LSI technology makes this approach a feasible and attractive candidate for use in a macrocomputer facility.
Index Terms:
Admissible maps, array processor, fast Fourier transform, grid computations, microprocessor array, n-cube array, parallel matrix multiplication, parallel processing, permutation network, switching network, triangular permutations, virtual array.
M.C., III Pease, "The Indirect Binary n-Cube Microprocessor Array," IEEE Transactions on Computers, vol. 26, no. 5, pp. 458-473, May 1977, doi:10.1109/TC.1977.1674863
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