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Tree Realizations of Iterative Circuits
April 1977 (vol. 26 no. 4)
pp. 365-383
| ASCII Text | x | ||
| S.H. Unger, "Tree Realizations of Iterative Circuits," IEEE Transactions on Computers, vol. 26, no. 4, pp. 365-383, April, 1977. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1977.1674846, author = {S.H. Unger}, title = {Tree Realizations of Iterative Circuits}, journal ={IEEE Transactions on Computers}, volume = {26}, number = {4}, issn = {0018-9340}, year = {1977}, pages = {365-383}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1977.1674846}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Tree Realizations of Iterative Circuits IS - 4 SN - 0018-9340 SP365 EP383 EPD - 365-383 A1 - S.H. Unger, PY - 1977 KW - Adders KW - binary adders KW - carry lookahead KW - combinational circuits KW - conditional sum KW - flow tables KW - high speed arithmetic units KW - iterative circuits KW - modular circuits KW - semi-groups KW - synthesis KW - tree circuits. VL - 26 JA - IEEE Transactions on Computers ER - | |||
It is shown how any combinational function that can be described by a flow table?or equivalently?is realizable in iterative form?can be realized in tree form. The propagation delay is then proportional to the logarithm of n, the number of inputs, while the logic complexity is a linear function of n. These results are related to various implementations of high-speed binary adders and a proposed new high-speed adder circuit.
Index Terms:
Adders, binary adders, carry lookahead, combinational circuits, conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, synthesis, tree circuits.
Citation:
S.H. Unger, "Tree Realizations of Iterative Circuits," IEEE Transactions on Computers, vol. 26, no. 4, pp. 365-383, April 1977, doi:10.1109/TC.1977.1674846
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