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Tree Realizations of Iterative Circuits
April 1977 (vol. 26 no. 4)
pp. 365-383
S.H. Unger, Department of Electrical Engineering and Computer Science, Columbia University
It is shown how any combinational function that can be described by a flow table?or equivalently?is realizable in iterative form?can be realized in tree form. The propagation delay is then proportional to the logarithm of n, the number of inputs, while the logic complexity is a linear function of n. These results are related to various implementations of high-speed binary adders and a proposed new high-speed adder circuit.
Index Terms:
Adders, binary adders, carry lookahead, combinational circuits, conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, synthesis, tree circuits.
Citation:
S.H. Unger, "Tree Realizations of Iterative Circuits," IEEE Transactions on Computers, vol. 26, no. 4, pp. 365-383, April 1977, doi:10.1109/TC.1977.1674846
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