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Shift Register Binary Rate Multipliers
March 1977 (vol. 26 no. 3)
pp. 276-278
| ASCII Text | x | ||
| W.H. Ninke, G.R. Ritchie, "Shift Register Binary Rate Multipliers," IEEE Transactions on Computers, vol. 26, no. 3, pp. 276-278, March, 1977. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1977.1674819, author = {W.H. Ninke and G.R. Ritchie}, title = {Shift Register Binary Rate Multipliers}, journal ={IEEE Transactions on Computers}, volume = {26}, number = {3}, issn = {0018-9340}, year = {1977}, pages = {276-278}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1977.1674819}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Shift Register Binary Rate Multipliers IS - 3 SN - 0018-9340 SP276 EP278 EPD - 276-278 A1 - W.H. Ninke, A1 - G.R. Ritchie, PY - 1977 KW - Binary rate multipliers (BRM's) KW - code conversion KW - logic design KW - shift registers KW - vector generation. VL - 26 JA - IEEE Transactions on Computers ER - | |||
Novel implementations of a binary rate multiplier (BRM) circuit are described. These BRM's, which use the input data word to load patterns into shift registers, are capable of working at higher speed than a conventional circuit, and should be more suitable for silicon integration. Long input data words can be accommodated with a long shift register or by interconnecting several short registers.
Index Terms:
Binary rate multipliers (BRM's), code conversion, logic design, shift registers, vector generation.
Citation:
W.H. Ninke, G.R. Ritchie, "Shift Register Binary Rate Multipliers," IEEE Transactions on Computers, vol. 26, no. 3, pp. 276-278, March 1977, doi:10.1109/TC.1977.1674819
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