This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Modeling and Digital Simulation for Design Verification and Diagnosis
December 1976 (vol. 25 no. 12)
pp. 1242-1253
S.A. Szygenda, Department of Electrical Engineering, University of Texas
There are many activities included under the category of design automation for integrated circuits. Some of these activities include packaging, placement, routing, interactive graphics, device data bases, and digital simulation; for the purpose of logic verification, timing analysis, and diagnostic test verification. One might also include high-level simulation, such as register transfer simulation, for the purpose of initial logic verification. This paper will be oriented towards modeling and implementation questions which arise when one is attempting to implement an extremely accurate digital simulator for the purposes of logic and design verification and fault simulation. Simulators for these purposes are now extremely important and occupy a major role in any design automation system. These systems are also very expensive and therefore the incorrect answers to a variety of questions which arise during the process of developing such simulators can be disastrous. This paper shall attempt to acquaint the reader with questions that have arisen over the years in terms of developing these simulators and what some of the possible answers are, and their respective tradeoffs. Although the successes, and, equally the failures, of many people have contributed to the present state of the art of digital simulators, one particular simulator, the one the authors are most intimately involved with, will be used as a source of detailed examples demonstrating many of the questions to be discussed.
Index Terms:
Data structures, design verification, digital logic simulation, fault diagnosis, fault simulation, functional simulation.
Citation:
S.A. Szygenda, E.W. Thompson, "Modeling and Digital Simulation for Design Verification and Diagnosis," IEEE Transactions on Computers, vol. 25, no. 12, pp. 1242-1253, Dec. 1976, doi:10.1109/TC.1976.1674591
Usage of this product signifies your acceptance of the Terms of Use.