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The Error Latency of a Fault in a Sequential Digital Circuit
June 1976 (vol. 25 no. 6)
pp. 655-659
J.J. Shedletsky, Digital Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University
In digital circuits there is typically a delay between the occurrence of a fault and the first error in the output. This delay is the error latency of the fault. A model to characterize the error latency of a fault in a sequential circuit is presented.
Index Terms:
Error latency, input probability, latency interval, Markov chain, random testing, sequential circuits.
Citation:
J.J. Shedletsky, E.J. McCluskey, "The Error Latency of a Fault in a Sequential Digital Circuit," IEEE Transactions on Computers, vol. 25, no. 6, pp. 655-659, June 1976, doi:10.1109/TC.1976.1674668
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