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Issue No.06 - June (1976 vol.25)
pp: 613-620
J.P. Hayes , Department of Electrical Engineering and the Computer Science Program, University of Southern California
ABSTRACT
Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed response sequence R bit by bit to the expected response Ro. The transition count (TC) of R, denoted c(R), is the number of times the signals forming R change value. In TC testing c(R) is recorded rather than R. A fault is detected if the observed TC c(R) differs from the correct TC c(Ro). This paper presents a formal analysis of TC testing. It is shown that the degree of detectability and distinguishability of faults obtainable by TC testing is less than that obtainable by conventional testing. t is argued that the TC tests should be constructed to maximize or minimize c(Ro). General methods are presented for constructing complete TC tests to detect both single and multiple stuck-line faults in combinational circuits. Optimal or near-optimal test sequences are derived for one-and two-level circuits. The use of TC testing for fault location is examined, and it is concluded that TC tests are relatively inefficient for this purpose.
INDEX TERMS
Combinational logic circuits, fault detection, fault diagnosis, minimal test sets, test generation, transition count (TC) testing.
CITATION
J.P. Hayes, "Transition Count Testing of Combinational Logic Circuits", IEEE Transactions on Computers, vol.25, no. 6, pp. 613-620, June 1976, doi:10.1109/TC.1976.1674661
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