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Truth-Table Verification of an Iterative Logic Array
June 1976 (vol. 25 no. 6)
pp. 605-613
F.J.O. Dias, Department of Electrical Engineering, Escola Polit?cnica, University of S?o Paulo
This paper studies the problem of fault detection in iterative logic arrays (ILA's) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number of cells can be faulty at any time. In this way, testing an array is equivalent to verifying the correctness of its truth table. That could be done exhaustively through the application of a set of tests whose size is exponential in N, the number of cells in the array. The procedure presented in this paper generates a test set whose size is constant (i.e., independent of the number N of cells in the array). Conditions (on the structure of the basic cell) for the application of this procedure are presented. A practical example illustrating the application of this procedure is presented. Bounds for the size of the derived test set are presented and it is shown how to modify the basic cell of an arbitrary array in order to test it with a constant number of tests.
Index Terms:
Adder, cell, checking experiment, fault detection, iterative array, multiple fault, test, truth table.
Citation:
F.J.O. Dias, "Truth-Table Verification of an Iterative Logic Array," IEEE Transactions on Computers, vol. 25, no. 6, pp. 605-613, June 1976, doi:10.1109/TC.1976.1674660
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