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Implementation of an Experimental Fault-Tolerant Memory System
June 1976 (vol. 25 no. 6)
pp. 557-568
| ASCII Text | x | ||
| W.C. Carter, C.E. McCarthy, "Implementation of an Experimental Fault-Tolerant Memory System," IEEE Transactions on Computers, vol. 25, no. 6, pp. 557-568, June, 1976. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1976.1674655, author = {W.C. Carter and C.E. McCarthy}, title = {Implementation of an Experimental Fault-Tolerant Memory System}, journal ={IEEE Transactions on Computers}, volume = {25}, number = {6}, issn = {0018-9340}, year = {1976}, pages = {557-568}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1976.1674655}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Implementation of an Experimental Fault-Tolerant Memory System IS - 6 SN - 0018-9340 SP557 EP568 EPD - 557-568 A1 - W.C. Carter, A1 - C.E. McCarthy, PY - 1976 KW - Decoding KW - diagnostics KW - encoding KW - error correction KW - error detection KW - fault-tolerant computing KW - memory with standby sparing KW - recovery KW - self-checking translators KW - switching algorithms. VL - 25 JA - IEEE Transactions on Computers ER - | |||
The experimental fault-tolerant memory system described in this paper has been designed to enable the modular addition of spares, to validate the theoretical fault-secure and self-testing properties of the translator/corrector, to provide a basis for experiments using the new testing and correction processes for recovery, and to determine the practicality of such systems. The hardware design and implementation are described, together with methods of fault insertion. The hardware/ software interface, including a restricted single error correction/double error detection (SEC/DED) code, is specified. Procedures are carefully described which, 1) test for specified physical faults, 2) ensure that single error corrections are not miscorrections due to triple faults, and 3) enable recovery from double errors.
Index Terms:
Decoding, diagnostics, encoding, error correction, error detection, fault-tolerant computing, memory with standby sparing, recovery, self-checking translators, switching algorithms.
Citation:
W.C. Carter, C.E. McCarthy, "Implementation of an Experimental Fault-Tolerant Memory System," IEEE Transactions on Computers, vol. 25, no. 6, pp. 557-568, June 1976, doi:10.1109/TC.1976.1674655
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