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Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
May 1976 (vol. 25 no. 5)
pp. 496-503
| ASCII Text | x | ||
| T. Lang, "Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network," IEEE Transactions on Computers, vol. 25, no. 5, pp. 496-503, May, 1976. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1976.1674637, author = {T. Lang}, title = {Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network}, journal ={IEEE Transactions on Computers}, volume = {25}, number = {5}, issn = {0018-9340}, year = {1976}, pages = {496-503}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1976.1674637}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network IS - 5 SN - 0018-9340 SP496 EP503 EPD - 496-503 A1 - T. Lang, PY - 1976 KW - Array processors KW - parallel processing KW - permutation networks KW - shuffle-exchange network. VL - 25 JA - IEEE Transactions on Computers ER - | |||
The shuffle-exchange network is considered as an interconnection network between processors and memory modules in an array computer. Lawrie showed that this network can be used to perform some important permutations in log2 N steps. This work is extended and a network is proposed that permits the realization of any permutation in 0([mi][/mi]N) shuffle-exchange steps. Additional modifications to th
Index Terms:
Array processors, parallel processing, permutation networks, shuffle-exchange network.
Citation:
T. Lang, "Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network," IEEE Transactions on Computers, vol. 25, no. 5, pp. 496-503, May 1976, doi:10.1109/TC.1976.1674637
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