Issue No.12 - December (1975 vol.24)
F.M. Brown , Department of Electrical Engineering, University of Kentucky
Any switching function has weighted representations, i.e., symmetric representations for which some of the arguments are repeated. We call a logic network based on such a representation a weighted realization. It is shown that a weighted realization may be implemented using a full-adder network (called a moment generator) whose outputs are fed to a multiplexer. A procedure is given to synthesize the full-adder network using the fewest possible modules and with strong coalescing of modules into multibit adders.
Binary adders, combinational logic, multiplexers, symmetric functions, tally-coded representations.
F.M. Brown, "Weighted Realizations of Switching Functions", IEEE Transactions on Computers, vol.24, no. 12, pp. 1217-1221, December 1975, doi:10.1109/T-C.1975.224166