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Synthesis and Comparison of Two's Complement Parallel Multipliers
October 1975 (vol. 24 no. 10)
pp. 1020-1027
| ASCII Text | x | ||
| J.A. Gibson, R.W. Gibbard, "Synthesis and Comparison of Two's Complement Parallel Multipliers," IEEE Transactions on Computers, vol. 24, no. 10, pp. 1020-1027, October, 1975. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1975.224117, author = {J.A. Gibson and R.W. Gibbard}, title = {Synthesis and Comparison of Two's Complement Parallel Multipliers}, journal ={IEEE Transactions on Computers}, volume = {24}, number = {10}, issn = {0018-9340}, year = {1975}, pages = {1020-1027}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1975.224117}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Synthesis and Comparison of Two's Complement Parallel Multipliers IS - 10 SN - 0018-9340 SP1020 EP1027 EPD - 1020-1027 A1 - J.A. Gibson, A1 - R.W. Gibbard, PY - 1975 KW - Algorithm syntheses KW - full adder arrays KW - multiplier comparisons KW - parallel binary multiplication KW - two's complement formulation. VL - 24 JA - IEEE Transactions on Computers ER - | |||
A machine word mathematical formulation is applied to analysis and synthesis of circuits for signed binary number multiplication. The circuits are related to each other and to contemporary circuit algorithms in the course of the syntheses and in a comparative discussion. Circuits with complemented multiplier/multiplicand (M?) or complemented partial product word (P?) corrections offer advantages in circuit symmetry and algorithmic structure.
Index Terms:
Algorithm syntheses, full adder arrays, multiplier comparisons, parallel binary multiplication, two's complement formulation.
Citation:
J.A. Gibson, R.W. Gibbard, "Synthesis and Comparison of Two's Complement Parallel Multipliers," IEEE Transactions on Computers, vol. 24, no. 10, pp. 1020-1027, Oct. 1975, doi:10.1109/T-C.1975.224117
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