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Synthesis and Comparison of Two's Complement Parallel Multipliers
October 1975 (vol. 24 no. 10)
pp. 1020-1027
J.A. Gibson, Department of Electrical Engineering, University of Canterbury
A machine word mathematical formulation is applied to analysis and synthesis of circuits for signed binary number multiplication. The circuits are related to each other and to contemporary circuit algorithms in the course of the syntheses and in a comparative discussion. Circuits with complemented multiplier/multiplicand (M?) or complemented partial product word (P?) corrections offer advantages in circuit symmetry and algorithmic structure.
Index Terms:
Algorithm syntheses, full adder arrays, multiplier comparisons, parallel binary multiplication, two's complement formulation.
Citation:
J.A. Gibson, R.W. Gibbard, "Synthesis and Comparison of Two's Complement Parallel Multipliers," IEEE Transactions on Computers, vol. 24, no. 10, pp. 1020-1027, Oct. 1975, doi:10.1109/T-C.1975.224117
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