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Analysis of Memory Interference in Multiprocessors
September 1975 (vol. 24 no. 9)
pp. 897-908
D.P. Bhandarkar, Texas Instruments,Incorporated
This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing time. The results predicted by the model are compared with some simulation results and some actual measurements on C.mmp, a multiprocessor system being built at Carnegie-Mellon University.
Index Terms:
Analytic models, Markov chains, memory interference, multiprocessors, performance measurement, simulation.
Citation:
D.P. Bhandarkar, "Analysis of Memory Interference in Multiprocessors," IEEE Transactions on Computers, vol. 24, no. 9, pp. 897-908, Sept. 1975, doi:10.1109/T-C.1975.224335
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