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Analysis of Memory Interference in Multiprocessors
September 1975 (vol. 24 no. 9)
pp. 897-908
| ASCII Text | x | ||
| D.P. Bhandarkar, "Analysis of Memory Interference in Multiprocessors," IEEE Transactions on Computers, vol. 24, no. 9, pp. 897-908, September, 1975. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1975.224335, author = {D.P. Bhandarkar}, title = {Analysis of Memory Interference in Multiprocessors}, journal ={IEEE Transactions on Computers}, volume = {24}, number = {9}, issn = {0018-9340}, year = {1975}, pages = {897-908}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1975.224335}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Analysis of Memory Interference in Multiprocessors IS - 9 SN - 0018-9340 SP897 EP908 EPD - 897-908 A1 - D.P. Bhandarkar, PY - 1975 KW - Analytic models KW - Markov chains KW - memory interference KW - multiprocessors KW - performance measurement KW - simulation. VL - 24 JA - IEEE Transactions on Computers ER - | |||
This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing time. The results predicted by the model are compared with some simulation results and some actual measurements on C.mmp, a multiprocessor system being built at Carnegie-Mellon University.
Index Terms:
Analytic models, Markov chains, memory interference, multiprocessors, performance measurement, simulation.
Citation:
D.P. Bhandarkar, "Analysis of Memory Interference in Multiprocessors," IEEE Transactions on Computers, vol. 24, no. 9, pp. 897-908, Sept. 1975, doi:10.1109/T-C.1975.224335
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