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July 1975 (vol. 24 no. 7)
pp. 695-700
H.D. Schnurmann, System Products Division, IBM Corporation
A heuristic method for generating large-scale integration (LSI) test patterns is described. In particular, this paper presents a technique for generating statistically random sequences to test complex logic circuits. The algorithms used to obtain a set of tests by means of weighted logic signal variations are included. Several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm. Also described is a means of obtaining a minimal number of test patterns. This approach has proved successful in obtaining fault-detecting patterns.
Index Terms:
Fault-detecting patterns, heuristic algorithm, large-scale integration, testing, testing algorithms, test-pattern generator, weighted random patterns.
Citation:
H.D. Schnurmann, E. Lindbloom, R.G. Carpenter, "The Weighted Random Test-Pattern Generator," IEEE Transactions on Computers, vol. 24, no. 7, pp. 695-700, July 1975, doi:10.1109/T-C.1975.224290
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