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P. Agrawal, Department of Electrical Engineering-Systems, University of Southern California
In this paper the random test generation method for large logic circuits is analyzed. Formulas for the detection probability and the number of random input patterns required to complete the test generation with a high probability are obtained for an irredundant fan-out-free combinational network tree consisting of identical n-input NAND gates. The quantitative estimates for the number of random input patterns required for test generation appear to depend upon the number of levels in the circuit and the fan-ins of the gates. Experimental results for actual computer logic circuits are given and show the validity of the approach.
Index Terms:
Combinational networks, detection probability, fault detection, path sensitizing, probabilistic analysis of logic, random test generation.
P. Agrawal, V.D. Agrawal, "Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks," IEEE Transactions on Computers, vol. 24, no. 7, pp. 691-695, July 1975, doi:10.1109/T-C.1975.224289
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