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Analysis of Logic Circuits with Faults Using Input Signal Probabilities
May 1975 (vol. 24 no. 5)
pp. 573578
ASCII Text  x  
K.P. Parker, E.J. McCluskey, "Analysis of Logic Circuits with Faults Using Input Signal Probabilities," IEEE Transactions on Computers, vol. 24, no. 5, pp. 573578, May, 1975.  
BibTex  x  
@article{ 10.1109/TC.1975.224264, author = {K.P. Parker and E.J. McCluskey}, title = {Analysis of Logic Circuits with Faults Using Input Signal Probabilities}, journal ={IEEE Transactions on Computers}, volume = {24}, number = {5}, issn = {00189340}, year = {1975}, pages = {573578}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1975.224264}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Analysis of Logic Circuits with Faults Using Input Signal Probabilities IS  5 SN  00189340 SP573 EP578 EPD  573578 A1  K.P. Parker, A1  E.J. McCluskey, PY  1975 KW  Boolean difference KW  fault detection KW  general combinational networks KW  input probability KW  iterative cells KW  output probability KW  probability KW  signal reliability KW  symmetric functions KW  test generation. VL  24 JA  IEEE Transactions on Computers ER   
A probabilistic treatment of general combinational networks has been developed. Using the notions of the probability of a signal and signal independence, algorithms have been presented to calculate the probability of the output of a logic circuit being 1. Simplifications to the algorithm result when sets of input probabilities are given the same value, and this process called bundling is described in the paper. Finally, a series of examples illustrate the application of the probabilistic approach to the analysis of faulty logic circuits.
Index Terms:
Boolean difference, fault detection, general combinational networks, input probability, iterative cells, output probability, probability, signal reliability, symmetric functions, test generation.
Citation:
K.P. Parker, E.J. McCluskey, "Analysis of Logic Circuits with Faults Using Input Signal Probabilities," IEEE Transactions on Computers, vol. 24, no. 5, pp. 573578, May 1975, doi:10.1109/TC.1975.224264
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