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Analysis of Logic Circuits with Faults Using Input Signal Probabilities
May 1975 (vol. 24 no. 5)
pp. 573-578
K.P. Parker, Digital Systems Laboratory, Stanford University
A probabilistic treatment of general combinational networks has been developed. Using the notions of the probability of a signal and signal independence, algorithms have been presented to calculate the probability of the output of a logic circuit being 1. Simplifications to the algorithm result when sets of input probabilities are given the same value, and this process called bundling is described in the paper. Finally, a series of examples illustrate the application of the probabilistic approach to the analysis of faulty logic circuits.
Index Terms:
Boolean difference, fault detection, general combinational networks, input probability, iterative cells, output probability, probability, signal reliability, symmetric functions, test generation.
Citation:
K.P. Parker, E.J. McCluskey, "Analysis of Logic Circuits with Faults Using Input Signal Probabilities," IEEE Transactions on Computers, vol. 24, no. 5, pp. 573-578, May 1975, doi:10.1109/T-C.1975.224264
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