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Design of Reliable Synchronous Sequential Circuits
May 1975 (vol. 24 no. 5)
pp. 567-570
D.H. Sawin, Communication/Automatic Data Processing Laboratory, U. S. Army Electronics Command
Fail-safe synchronous sequential machines produce safeside outputs when failures occur within the machine. This correspondence presents a procedure to design such machines using a modification of the on-set equation form originally presented by Tohma et al. [1] and later improved by Diaz et al. [2]. A systematic procedure for state assignment and next-state equation derivation, using partition theory, is presented. From this method an easily calculated upper bound on the number of gates required-to realize a fail-safe circuit is derived.
Index Terms:
Fail-safe design, fault-detection, reliable design, state assignments, synchronous sequential machine design.
Citation:
D.H. Sawin, "Design of Reliable Synchronous Sequential Circuits," IEEE Transactions on Computers, vol. 24, no. 5, pp. 567-570, May 1975, doi:10.1109/T-C.1975.224262
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