Issue No.05 - May (1975 vol.24)
Advances in integrated circuit technology are decreasing acquisition cost per function of digital hardware while system software costs are increasing. The hardware advances allow practical implementation of more sophisticated and complex systems which have fewer components, but which may present severe test and maintenance problems due to their complexity. As a result, the use of built-in test (BIT) hardware in place of software becomes increasingly attractive. The Navy funded Advanced Avionics Fault Isolation System (AAFIS) concept utilizes BIT logic for cost-effective fault detection and fault isolation to a digital subsystem and to the faulty module therein. Added logic, available at low cost with advanced microelectronics, is used to perform test pattern generation in each subsystem and to code over the test sequence the outputs and test points on each subsystem module. The coded test response is compared to a predetermined constant. The OR of resulting module pass-fail signals indicates subsystem faults, while identification of a module fail signal provides isolation to a faulty module. Practical coding techniques are presented, with tradeoff of speed, test effectiveness and logic requirements for each. BIT logic design and simulation results verify high fault detection and moderate added logic for BIT.
Automatic test equipment (ATE), built-in test (BIT), fault isolation, large-scale integration (LSI) testing, self test, subsystem test, system maintenance, test response.
D.F. Calhoun, G.E. Alderson, J.E. Bauer, C.T. Joeckel, "An Advanced Fault Isolation System for Digital Logic", IEEE Transactions on Computers, vol.24, no. 5, pp. 489-497, May 1975, doi:10.1109/T-C.1975.224251