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Fault Masking in Combinational Logic Circuits
May 1975 (vol. 24 no. 5)
pp. 476-482
F.J.O. Dias, Digital Systems Laboratory, Stanford University
An important problem in fault detection is to verify whether a single-fault test set is able to detect all multiple-faults. This paper provides a solution to the above problem. It is known that a test set derived for the detection of some fault may fail this purpose in the presence of an additional fault. This phenomenon is called masking among faults, and is of great importance in the derivation of a test set which detects all multiple-faults. This paper investigates the masking relations among faults in a combinational logic circuit. For this purpose a transform for the circuit is defined and a model for fault analysis is constructed. This transform and model reduce the number of faults which have to be considered in order to achieve the detection of all multiple-faults. An algebraic procedure yields the derivation of the masking relations. A problem which arises, namely the existence of a set of faults forming a loop of masking relations is considered. An application is presented: starting with a test set derived under the single-fault assumption it is shown how to extend this test set so that it detects all multiple-faults. All of the results in this paper are valid for general multiple-output circuits. For simplicity in the exposition, the single-output case is examined.
Index Terms:
Combinational logic circuit, fault detection, fault masking, masking loop, multiple-fault, single-fault, test.
Citation:
F.J.O. Dias, "Fault Masking in Combinational Logic Circuits," IEEE Transactions on Computers, vol. 24, no. 5, pp. 476-482, May 1975, doi:10.1109/T-C.1975.224249
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