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Hazard Correction in Synchronous Sequential Circuits
March 1975 (vol. 24 no. 3)
pp. 305-310
M. Servit, Department of Computers, Electrotechnical Faculty, Czech Polytechnical Institute
Limitations which are placed on input and clock signals of single and double-rank synchronous sequential circuits with memory composed of level-triggered flip-flops are presented and compared with the results of Unger [1] and Curtis [2].
Index Terms:
Double-rank circuit, flip-flop memory, hazard correction, single-rank circuit, synchronous sequential circuit.
Citation:
M. Servit, "Hazard Correction in Synchronous Sequential Circuits," IEEE Transactions on Computers, vol. 24, no. 3, pp. 305-310, March 1975, doi:10.1109/T-C.1975.224211
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