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Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers
March 1975 (vol. 24 no. 3)
pp. 250-258
M.I. Elmasry, Department of Electrical Engineering, University of Waterloo
Logic-in-memory (LIM) organization allows central processor functions of computing systems to be combined with memory in regular arrays. The cells of these arrays can themselves be constructed regularly and economically using similar two-level emitter-function logic (EFL) structures. The structure is a development of current-mode logic and it permits the large-scale integration (LSI) realization of three levels of logic with similar silicon area and power dissipation to a single conventional emitter-coupled logic (ECL) gate. It also permits the realization of a D latch in a single structure. The capability of the structure is demonstrated in examples of LIM data transfer and sorting arrays.
Index Terms:
Current-mode logic, emitter-function logic (EFL), high-speed realization, large-scale integration (LSI), logic-in memory (LIM) computers, multiemitter two-level structures (METTL).
Citation:
M.I. Elmasry, P.M. Thompson, "Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers," IEEE Transactions on Computers, vol. 24, no. 3, pp. 250-258, March 1975, doi:10.1109/T-C.1975.224206
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