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Y. Tohma, Department of Electronics, Tokyo Institute of Technology
A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.
Index Terms:
Fail-safe, fault, flip-flop, reliable system, sequential circuit.
Citation:
Y. Tohma, "Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory," IEEE Transactions on Computers, vol. 23, no. 11, pp. 1149-1154, Nov. 1974, doi:10.1109/T-C.1974.223822
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