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November 1974 (vol. 23 no. 11)
pp. 1132-1138
A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. Th
Index Terms:
Deductive simulation method, fault diagnosis, fault simulation, logic design verification, parallel simulation method.
Citation:
H.Y.-P. Chang, S.G. Chappell, C.H. Elmendorf, L.D. Schmidt, "Comparison of Parallel and Deductive Fault Simulation Methods," IEEE Transactions on Computers, vol. 23, no. 11, pp. 1132-1138, Nov. 1974, doi:10.1109/T-C.1974.223820
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