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Issue No.07 - July (1974 vol.23)
pp: 727-735
J.P. Hayes , Department of Electrical Engineering and Computer Science Program, University of Southern California
ABSTRACT
The problem of selecting test points to reduce the number of tests for fault detection in combinational logic networks is examined. A method is presented for labeling the lines of a network. Procedures are described for obtaining a minimal labeling, i.e., one corresponding to a minimal set of tests, for fanout-free circuits and for a restricted class of circuits with fanout. Using these procedures, a branch-and-bound algorithm is developed for selecting an optimal (or near-optimal) set of q test points in fanout-free networks. Some difficulties associated with test point placement in general networks are pointed out. It is shown that the labeling approach is also applicable to the problem of selecting and placing control logic.
INDEX TERMS
Control logic, fault detection, improving diagnosability, placement algorithms, test points.
CITATION
J.P. Hayes, A.D. Friedman, "Test Point Placement to Simplify Fault Detection", IEEE Transactions on Computers, vol.23, no. 7, pp. 727-735, July 1974, doi:10.1109/T-C.1974.224021
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