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D.A. Sheppard, Z.G. Vranesic, "Fault Detection of Binary Sequential Machines Using R-Valued Test Machines," IEEE Transactions on Computers, vol. 23, no. 4, pp. 352-358, April, 1974.
 
 
BibTex
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@article{ 10.1109/T-C.1974.223949,
author = {D.A. Sheppard and Z.G. Vranesic},
title = {Fault Detection of Binary Sequential Machines Using R-Valued Test Machines},
journal ={IEEE Transactions on Computers},
volume = {23},
number = {4},
issn = {0018-9340},
year = {1974},
pages = {352-358},
doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1974.223949},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Fault Detection of Binary Sequential Machines Using R-Valued Test Machines
IS - 4
SN - 0018-9340
SP352
EP358
EPD - 352-358
A1 - D.A. Sheppard,
A1 - Z.G. Vranesic,
PY - 1974
KW - Fault detection
KW - many-valued logic
KW - permutation inputs
KW - synchronous sequential machines
KW - test machines.
VL - 23
JA - IEEE Transactions on Computers
ER -
 
D.A. Sheppard, Cybernetic Services, Canadian National Railway
An improved method for detection of faults in completely specified synchronous sequential machines is described. The technique is algorithmic, based on the concept of embedding the given binary machine into an easily testable R-valued machine. Heuristic optimization of additional permutation inputs is shown to lead to considerable reduction in the length of the fault sequence. A bound on the sequence length is derived, which in most cases is significantly lower than those of comparable methods.
Index Terms:
Fault detection, many-valued logic, permutation inputs, synchronous sequential machines, test machines.
Citation:
D.A. Sheppard, Z.G. Vranesic, "Fault Detection of Binary Sequential Machines Using R-Valued Test Machines," IEEE Transactions on Computers, vol. 23, no. 4, pp. 352-358, April 1974, doi:10.1109/T-C.1974.223949
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