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March 1974 (vol. 23 no. 3)
pp. 327
V.C. Hamacher, Department of Electrical Engineering and Computer Science, University of Toronto
The main point made in the above comment, namely, that in our division array [1] only one row of the array is actively performing processing at any one time, is well taken. This leads to the reasonable conclusion that serially reusing a single row of logic, enabled by temporary storage of the partial remainder, leads to only a small (about 25 percent) speed degradation accompanied by substantial cost savings.
Citation:
V.C. Hamacher, M. Cappa, "Authors' Reply2," IEEE Transactions on Computers, vol. 23, no. 3, pp. 327, March 1974, doi:10.1109/T-C.1974.223932
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