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A Multiple-Stream Registerless Shared-Resource Processor
March 1974 (vol. 23 no. 3)
pp. 277-285
E.F. Miller, General Research Corporation
A novel high-performance processor architecture for processing a large number of independent instruction streams is proposed and its operating behavior studied. The proposed processor operates on instruction words in a two-address format (thereby eliminating the "operating registers"), and is organized in a fashion which permits as high degree of internal buffering and pipelining. The processor has the following properties: 1) The hardware cost grows only slightly more than linearly with the overall implementation cost; 2) The overall performance is primarily dependent on the processor wordtime and is only secondarily dependent on the supporting memory cycle time; 3) All instruction stream interfaces with memory occur at special queuing (buffer) units which are used to "unscramble" the instruction streams and continually provide work for subsequent processing elements.
Index Terms:
Computer architecture, computer instruction stream models, multiple instruction stream, multiple data stream (MIMD) queued instruction processing, resource-sharing, two-address format.
E.F. Miller, "A Multiple-Stream Registerless Shared-Resource Processor," IEEE Transactions on Computers, vol. 23, no. 3, pp. 277-285, March 1974, doi:10.1109/T-C.1974.223923
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