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February 1974 (vol. 23 no. 2)
pp. 153-165
S. Yajima, Department of Information Science, Kyoto University
As a method for greatly reducing power dissipation in logic networks, we propose some logic organization techniques for logic networks. By such techniques, their power dissipation is to be minimized under certain input conditions, or the average power dissipation in the whole network should be minimized. A logic network in which these problems are taken into account will be called a power minimized logic circuit (PML).
Index Terms:
Asymmetrically power dissipating element, LSI, minimum power realization, NAND gate, positive (negative) loop, power dissipation in logic networks, power minimization problem, power minimized logic circuit (PML), zero power realization.
Citation:
S. Yajima, K. Inagaki, "Power Minimization Problems of Logic Networks," IEEE Transactions on Computers, vol. 23, no. 2, pp. 153-165, Feb. 1974, doi:10.1109/T-C.1974.223878
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