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On-Set Realization of Fail-Safe Sequential Machines
February 1974 (vol. 23 no. 2)
pp. 133-138
M. Diaz, Laboratoire d'Automatique et d'Analyse des Syst?mes
Fail-safe sequential machines can be constructed in such a way that if a failure happens in the sequential part, the ulterior functioning must carry on outside the code chosen to represent the set of states. This paper presents a study of the failures in the input combinational circuit and of the feasibility conditions of sequential machines with states coded by a k-out-of-n code. The electronic circuit is realized in a classical way (on-set realization) and must obey two hypotheses, 1) no failure on clock line C, and 2) single fault (stuck at 0 or stuck at 1) on other connections than C.
Index Terms:
Constraining set, fail-safe sequential machines, k-out-of-n code, on-set realization, predecessor set.
Citation:
M. Diaz, J.C. Geffroy, M. Courvoisier, "On-Set Realization of Fail-Safe Sequential Machines," IEEE Transactions on Computers, vol. 23, no. 2, pp. 133-138, Feb. 1974, doi:10.1109/T-C.1974.223875
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