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Optimal One-Bit Full Adders With Different Types of Gates
January 1974 (vol. 23 no. 1)
pp. 63-70
| ASCII Text | x | ||
| null Tso-Kai Liu, K.R. Hohulin, null Lih-Er Shiau, S. Muroga, "Optimal One-Bit Full Adders With Different Types of Gates," IEEE Transactions on Computers, vol. 23, no. 1, pp. 63-70, January, 1974. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1974.223778, author = {null Tso-Kai Liu and K.R. Hohulin and null Lih-Er Shiau and S. Muroga}, title = {Optimal One-Bit Full Adders With Different Types of Gates}, journal ={IEEE Transactions on Computers}, volume = {23}, number = {1}, issn = {0018-9340}, year = {1974}, pages = {63-70}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1974.223778}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Optimal One-Bit Full Adders With Different Types of Gates IS - 1 SN - 0018-9340 SP63 EP70 EPD - 63-70 A1 - null Tso-Kai Liu, A1 - K.R. Hohulin, A1 - null Lih-Er Shiau, A1 - S. Muroga, PY - 1974 KW - Implicit enumeration KW - integer programming KW - one-bit adder KW - optimal networks. VL - 23 JA - IEEE Transactions on Computers ER - | |||
Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder. Optimality is derined as the minimization of the number of gates under different restrictions.
Index Terms:
Implicit enumeration, integer programming, one-bit adder, optimal networks.
Citation:
null Tso-Kai Liu, K.R. Hohulin, null Lih-Er Shiau, S. Muroga, "Optimal One-Bit Full Adders With Different Types of Gates," IEEE Transactions on Computers, vol. 23, no. 1, pp. 63-70, Jan. 1974, doi:10.1109/T-C.1974.223778
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