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| S.M. Reddy, "Complete Test Sets for Logic Functions," IEEE Transactions on Computers, vol. 22, no. 11, pp. 1016-1020, November, 1973. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1973.223638, author = {S.M. Reddy}, title = {Complete Test Sets for Logic Functions}, journal ={IEEE Transactions on Computers}, volume = {22}, number = {11}, issn = {0018-9340}, year = {1973}, pages = {1016-1020}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1973.223638}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Complete Test Sets for Logic Functions IS - 11 SN - 0018-9340 SP1016 EP1020 EPD - 1016-1020 A1 - S.M. Reddy, PY - 1973 KW - Complete test sets KW - expanded truth table KW - fault detecting test sets KW - logic networks KW - multiple stuck-at-faults KW - restricted gate networks KW - stuck-at-faults KW - unate gate networks. VL - 22 JA - IEEE Transactions on Computers ER - | |||
The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid.
Index Terms:
Complete test sets, expanded truth table, fault detecting test sets, logic networks, multiple stuck-at-faults, restricted gate networks, stuck-at-faults, unate gate networks.
Citation:
S.M. Reddy, "Complete Test Sets for Logic Functions," IEEE Transactions on Computers, vol. 22, no. 11, pp. 1016-1020, Nov. 1973, doi:10.1109/T-C.1973.223638
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