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| ASCII Text | x | ||
| M.R. Paige, "Synthesis of Diagnosable FET Networks," IEEE Transactions on Computers, vol. 22, no. 5, pp. 513-516, May, 1973. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1973.223754, author = {M.R. Paige}, title = {Synthesis of Diagnosable FET Networks}, journal ={IEEE Transactions on Computers}, volume = {22}, number = {5}, issn = {0018-9340}, year = {1973}, pages = {513-516}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1973.223754}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Synthesis of Diagnosable FET Networks IS - 5 SN - 0018-9340 SP513 EP516 EPD - 513-516 A1 - M.R. Paige, PY - 1973 KW - Fault diagnosis KW - FET network KW - irredundant function KW - network synthesis KW - single and multiple faults. VL - 22 JA - IEEE Transactions on Computers ER - | |||
With the advent of field-effect transistor (FET) technology it has become practical and economical to employ complex functions as network primitives. This paper describes a synthesis procedure for diagnosable (all single and multiple faults can be detected) FET networks. A companion procedure for generating tests to detect all faults in the resulting network is also described. This methodology does not guarantee the minimality of the network, however, it is intuitively understandable and easy to apply.
Index Terms:
Fault diagnosis, FET network, irredundant function, network synthesis, single and multiple faults.
Citation:
M.R. Paige, "Synthesis of Diagnosable FET Networks," IEEE Transactions on Computers, vol. 22, no. 5, pp. 513-516, May 1973, doi:10.1109/T-C.1973.223754
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