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Shared Logic Realizations of Dynamically Self-Checked and Fault-Tolerant Logic
March 1973 (vol. 22 no. 3)
pp. 298-306
M.Y. Osman, General Telephone and Electronics Laboratories, Waltham Research Center
Dynamically self-checked or fault-tolerant realizations of switching functions and sequential machines are proposed under a fault model that permits arbitrary logic faults in a single-logic module, where the modules are explicitly defined. These realizations permit considerable logic sharing, organized around an (n, m, r)-basis for decomposing switching functions. The logic sharing permits more economical realizations than can be obtained using classical parity and triple-modular redundancy schemes for obtaining logic circuits with the corresponding property.
Index Terms:
Combinational logic, fault-tolerant logic, parity, redundancy, reliability, self-checking logic, sequential machines, single-module faults, triple-modular redundancy.
Citation:
M.Y. Osman, C.D. Weiss, "Shared Logic Realizations of Dynamically Self-Checked and Fault-Tolerant Logic," IEEE Transactions on Computers, vol. 22, no. 3, pp. 298-306, March 1973, doi:10.1109/T-C.1973.223710
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