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February 1973 (vol. 22 no. 2)
pp. 172-175
M. Cappa, Collins Radio Company
An augmented iterative array for binary division (IAD), is described. It uses carry-save reduction and carry-look-ahead principles to achieve high speed. Logic cost and speed comparisons with two other design techniques are presented. An 8-bit prototype model that operates in under 500 ns has been built from commercially available high-speed MSI TTL integrated circuits to verify the feasibility of the IAD scheme.
Index Terms:
Division network, iterative array, nonrestoring division.
Citation:
M. Cappa, V.C. Hamacher, "An Augmented Iterative Array for High-Speed Binary Division," IEEE Transactions on Computers, vol. 22, no. 2, pp. 172-175, Feb. 1973, doi:10.1109/T-C.1973.223680
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