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February 1973 (vol. 22 no. 2)
pp. 172-175
| ASCII Text | x | ||
| M. Cappa, V.C. Hamacher, "An Augmented Iterative Array for High-Speed Binary Division," IEEE Transactions on Computers, vol. 22, no. 2, pp. 172-175, February, 1973. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1973.223680, author = {M. Cappa and V.C. Hamacher}, title = {An Augmented Iterative Array for High-Speed Binary Division}, journal ={IEEE Transactions on Computers}, volume = {22}, number = {2}, issn = {0018-9340}, year = {1973}, pages = {172-175}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1973.223680}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - An Augmented Iterative Array for High-Speed Binary Division IS - 2 SN - 0018-9340 SP172 EP175 EPD - 172-175 A1 - M. Cappa, A1 - V.C. Hamacher, PY - 1973 KW - Division network KW - iterative array KW - nonrestoring division. VL - 22 JA - IEEE Transactions on Computers ER - | |||
An augmented iterative array for binary division (IAD), is described. It uses carry-save reduction and carry-look-ahead principles to achieve high speed. Logic cost and speed comparisons with two other design techniques are presented. An 8-bit prototype model that operates in under 500 ns has been built from commercially available high-speed MSI TTL integrated circuits to verify the feasibility of the IAD scheme.
Index Terms:
Division network, iterative array, nonrestoring division.
Citation:
M. Cappa, V.C. Hamacher, "An Augmented Iterative Array for High-Speed Binary Division," IEEE Transactions on Computers, vol. 22, no. 2, pp. 172-175, Feb. 1973, doi:10.1109/T-C.1973.223680
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