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Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
January 1973 (vol. 22 no. 1)
pp. 46-60
M.J.Y. Williams, InternationalComputers, Ltd.
With the increasing complexity of logic that can be fabricated on a single large-scale integrated (LSI) circuit chip, there is a growing problem of checking the logical behavior of the chips at manufacture. The problem is particularly acute for sequential circuits, where there are difficulties in setting and checking the state of the system.
Index Terms:
Added logic for testability, circuit testing, diagnosis, LSI, test generation, test points.
Citation:
M.J.Y. Williams, J.B. Angell, "Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic," IEEE Transactions on Computers, vol. 22, no. 1, pp. 46-60, Jan. 1973, doi:10.1109/T-C.1973.223600
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