This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Easily Testable Realizations ror Logic Functions
November 1972 (vol. 21 no. 11)
pp. 1183-1188
S.M. Reddy, Department of Electrical Engineering, University of Iowa
Desirable properties of "easily testable networks" are given. A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties. If only permanent stuck-at-0 (s-a-0) or stuck-at-1 (s-a-1) faults occur in a single AND gate or only a single EXCLUSIVE-OR gate is faulty, the following results are derived on fault detecting test sets for the proposed networks: 1) only (n/4) tests, independent of the function being realized, are required if the primary inputs are fault-free; 2) only 2n, additional inputs (which depend on the function realized) are required if the primary inputs can be faulty, where n, is the number of variables appearing in even number of product terms in the Reed-Muller canonical expansion of the function; and 3) the additional 2ne inputs are not required if the network is provided with an observable point at the output of an extra AND gate.
Index Terms:
Easily testable networks, fault detection, Reed-Muller canonic expressions, single faults, stuck-at-faults.
Citation:
S.M. Reddy, "Easily Testable Realizations ror Logic Functions," IEEE Transactions on Computers, vol. 21, no. 11, pp. 1183-1188, Nov. 1972, doi:10.1109/T-C.1972.223475
Usage of this product signifies your acceptance of the Terms of Use.