Issue No.05 - May (1972 vol.21)
R.T. Chien , Department of Electrical Engineering, Research Laboratory of Electronics, Massachusetts Institute of Technology
In high-speed multipliers, multiplication is activated by processing a group of bits in parallel. As a result, any defects in circuitry produce possible errors in positions that are separated by fixed periods. A class of codes for the correction of such iterative error patterns resulting from a single fault is presented in this paper. A decoding algorithm together with a simple implementation scheme is also discussed.
Arithmetic codes, computer reliability, error correction in high-speed computation, error detection and correction, fault tolerant computing.
R.T. Chien, null Se June Hong, "Error Correction in High-Speed Arithmetic", IEEE Transactions on Computers, vol.21, no. 5, pp. 433-438, May 1972, doi:10.1109/T-C.1972.223538