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On the Tradeoff Between Logic Performance and Circuit-to-Pin Ratio for LSI
February 1972 (vol. 21 no. 2)
pp. 147-153
Roy L. Russo, IBM T. J. Watson Research Center, Yorktown Heights, N. Y. 10598.
A key problem in the effective use of large-scale integration is the design and partitioning of computer logic to achieve sufficiently high circuit-to-pin ratios. In this paper a power-law relationship between pins and partitioned circuits is discussed and empirical evidence is presented that implies that the pin requirement is a sensitive function of the performance level of the logic. Two techniques for increasing the circuit-to-pin ratio are discussed. The first is to serialize the interchip transfer of information that results in a degradation in performance of the logic. The second is to encode the information to be transferred so that fewer pins are required but without reducing the performance. The results of experiments using the encoding principle to map a small logic graph onto chips are presented to obtain an indication of the effectiveness of this technique. It is shown that the relationship between circuits and pins when using encoding remains a power law.
Citation:
Roy L. Russo, "On the Tradeoff Between Logic Performance and Circuit-to-Pin Ratio for LSI," IEEE Transactions on Computers, vol. 21, no. 2, pp. 147-153, Feb. 1972, doi:10.1109/TC.1972.5008919
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