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Asynchronous Arbiters
January 1972 (vol. 21 no. 1)
pp. 37-42
| ASCII Text | x | ||
| W.W. Plummer, "Asynchronous Arbiters," IEEE Transactions on Computers, vol. 21, no. 1, pp. 37-42, January, 1972. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1972.223429, author = {W.W. Plummer}, title = {Asynchronous Arbiters}, journal ={IEEE Transactions on Computers}, volume = {21}, number = {1}, issn = {0018-9340}, year = {1972}, pages = {37-42}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1972.223429}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Asynchronous Arbiters IS - 1 SN - 0018-9340 SP37 EP42 EPD - 37-42 A1 - W.W. Plummer, PY - 1972 KW - Asynchronous arbiter KW - asynchronous logic design KW - conflict resolution KW - functional unit allocation KW - hardware resource allocation KW - macromodules KW - modular control logic KW - multiprocessor computer system KW - priority network KW - sequential machines with multiple input changes. VL - 21 JA - IEEE Transactions on Computers ER - | |||
When two or more processors attempt to simultaneously use a functional unit (memory, multiplier, etc.), an arbiter module must be employed to insure that processor requests are honored in sequence. The design of asynchronous arbiters is complicated because multiple input changes are allowed, and because inputs may change even if the circuit is not in a stable state. A practical arbiter and its implementation are presented. Implementation of various priority rules (linear, ring, mixed) is discussed, and building large arbiters with trees of two-user arbiters is considered.
Index Terms:
Asynchronous arbiter, asynchronous logic design, conflict resolution, functional unit allocation, hardware resource allocation, macromodules, modular control logic, multiprocessor computer system, priority network, sequential machines with multiple input changes.
Citation:
W.W. Plummer, "Asynchronous Arbiters," IEEE Transactions on Computers, vol. 21, no. 1, pp. 37-42, Jan. 1972, doi:10.1109/T-C.1972.223429
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