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Issue No.01 - January (1972 vol.21)
pp: 21-30
S.Y.H. Su , Department of Electrical Engineering, University of Southern California
ABSTRACT
A systematic approach to the location of a single failure in a combinational logic network is presented. The method utilizes only the required tests and needs no fault table. The structure of the logic network is taken into consideration when selecting the tests to be applied. For tree networks, we start from the gate that generates a primary output and sequentially trace back through the stages of the network according to a fixed set of rules. At each stage we either locate the fault or determine the direction of the trace.
INDEX TERMS
Combinational logic, diagnosis algorithms, diagnostic test generation, error diagnosis, fault location, logic circuit diagnosis, sensitized faults, testing, tree networks, undistinguishable faults.
CITATION
S.Y.H. Su, null Yun-Chung Cho, "A New Approach to the Fault Location of Combinational Circuits", IEEE Transactions on Computers, vol.21, no. 1, pp. 21-30, January 1972, doi:10.1109/T-C.1972.223427
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