CSDL - IEEE Transactions on Computers

IEEE Transactions on Computers - Table of contents (PDF)

pp. c1-1435-c

IEEE Computer Society (PDF)

pp. c2

Fault-Tolerant Computing: An Introduction and an Overview (Abstract)

C.V. Ramamoorthy, IEEE

pp. 1241-1244

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An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits (Abstract)

S.S. Yau, IEEE

null Yu-Shan Tang

pp. 1245-1251

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Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks (Abstract)

D.C. Bossen, IEEE

null Se June Hong

pp. 1252-1257

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Algorithms for Detection of Faults in Logic Circuits (Abstract)

W.G. Bouricius, IEEE

C. Tan

pp. 1258-1264

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Derivation of Minimum Test Sets for Unate Logical Circuits (Abstract)

R. Betancourt, IEEE

pp. 1264-1269

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Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code (Abstract)

pp. 1270-1275

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Structural Factors in the Fault Diagnosis of Combinational Networks (Abstract)

J.D. Russell, IEEE

C.R. Kime

pp. 1276-1285

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Fault Equivalence in Combinational Logic Networks (Abstract)

E.J. McCluskey, IEEE

F.W. Clegg

pp. 1286-1293

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Computer Diagnosis Using the Blocking Gate Approach (Abstract)

C.V. Ramamoorthy, IEEE

W. Mayeda

pp. 1294-1299

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Logic Design for Dynamic and Interactive Recovery (Abstract)

W.C. Carter, IEEE

pp. 1300-1305

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Reliability Modeling for Fault-Tolerant Computers (Abstract)

W.G. Bouricius, IEEE

pp. 1306-1311

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The STAR (Self-Testing And Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design (Abstract)

A. Avizienis, IEEE

pp. 1312-1321

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Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design (Abstract)

A. Avizienis, IEEE

pp. 1322-1331

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Proving Programs to be Correct (PDF)

J.C. King

pp. 1331-1336

Soviet Progress in the Design of Fault-Tolerant Digital Machines (PDF)

R.A. Short, IEEE

J. Goldberg

pp. 1337-1352

On the Design of Minimum Length Fault Tests for Combinational Circuits (PDF)

L.W. Bearnson, IEEE

C.C. Carroll

pp. 1353-1356

Boolean Difference for Fault Detection in Asynchronous Sequential Machines (Abstract)

M.Y. Hsiao, IEEE

D.K. Chia

pp. 1356-1361

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On the Design of Multiple Fault Diagnosable Networks (PDF)

D.R. Schertz, IEEE

G. Metze

pp. 1361-1364

A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits (PDF)

M.A. Breuer, IEEE

pp. 1364-1370

A Method for Redundancy Scheme Performance Assessment (Abstract)

T.F. Klaschka

pp. 1371-1376

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On Reliability Modeling and Analysis of Ultrareliable Fault-Tolerant Digital Systems (Abstract)

F.P. Mathur, IEEE

pp. 1376-1382

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The MECRA: A Self-Reconfigurable Computer for Highly Reliable Process (Abstract)

F.P. Maison

pp. 1382-1388

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A Three-Failure-Tolerant Computer System (Abstract)

L.J. Koczela, IEEE

pp. 1389-1393

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A Fault-Tolerant Information Processing Concept for Space Vehicles (PDF)

A.L. Hopkins, IEEE

pp. 1394-1403

Analysis of Parallel Systems (Abstract)

T.H. Bredt, IEEE

pp. 1403-1407

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Locatability of Faults in Combinational Networks (Abstract)

F.G. Gray, IEEE

J.F. Meyer

pp. 1407-1412

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A Simple Self-Testing Decoder Checking Circuit (Abstract)

pp. 1413-1414

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Contributors (PDF)

pp. 1415-1419

Blank Page (PDF)

pp. 1435

Information for Authors (PDF)

pp. 1435