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Gate-Interconnection Minimization of Switching Networks Using Negative Gates
June 1971 (vol. 20 no. 6)
pp. 698-706
T. Ibaraki, IEEE
In this note, we develop an algorithm to design a two-level switching network composed of negative gates with no fan-in restriction imposed on them. The resulting network is such that it minimizes the cost function h(G, 1), a monotone nondecreasing function of G and I, where G is the total number of gates and I is the total number of interconnections in the network. In other words, the earlier work is generalized so that the number of interconnections may be included in its cost criterion. The algorithm is then extended to the multiple output network design.
Index Terms:
Compatible sets, gate-interconnection minimization, MOS integrated circuits, multiple output networks, negative gates, set covering problems, switching networks, two-level networks.
Citation:
T. Ibaraki, "Gate-Interconnection Minimization of Switching Networks Using Negative Gates," IEEE Transactions on Computers, vol. 20, no. 6, pp. 698-706, June 1971, doi:10.1109/T-C.1971.223331
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