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A Heuristic Algorithm for the Testing of Asynchronous Circuits
June 1971 (vol. 20 no. 6)
pp. 639-647
This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given.
Index Terms:
Circuit testing, D-algorithm, diagnosis, LSI, simulation, test generation.
Citation:
G.R. Putzolu, J.P. Roth, "A Heuristic Algorithm for the Testing of Asynchronous Circuits," IEEE Transactions on Computers, vol. 20, no. 6, pp. 639-647, June 1971, doi:10.1109/T-C.1971.223315
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