Issue No.04 - April (1971 vol.20)
S.D. Pezaris , IEEE
A high-speed array multiplier generating the full 34-bit product of two 17-bit signed (2's complement) numbers in 40 ns is described. The multiplier uses a special 2-bit gated adder circuit with anticipated carry. Negative numbers are handled by considering their highest order bit as negative, all other bits as positive, and adding negative partial products directly through appropriate circuits. The propagation of sum and carry signals is such that sum delays do not significantly contribute to the overall multiplier delay.
Array multiplier, Dadda's multiplier, digital multiplier, fast multiplier, parallel multiplier, Wallace's multiplier.
S.D. Pezaris, "A 40-ns 17-Bit by 17-Bit Array Multiplier", IEEE Transactions on Computers, vol.20, no. 4, pp. 442-447, April 1971, doi:10.1109/T-C.1971.223261