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Variable-Mode Counting with Straight Binary Counters
January 1971 (vol. 20 no. 1)
pp. 97-98
| ASCII Text | x | ||
| J.S. Byrd, "Variable-Mode Counting with Straight Binary Counters," IEEE Transactions on Computers, vol. 20, no. 1, pp. 97-98, January, 1971. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1971.223086, author = {J.S. Byrd}, title = {Variable-Mode Counting with Straight Binary Counters}, journal ={IEEE Transactions on Computers}, volume = {20}, number = {1}, issn = {0018-9340}, year = {1971}, pages = {97-98}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1971.223086}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Variable-Mode Counting with Straight Binary Counters IS - 1 SN - 0018-9340 SP97 EP98 EPD - 97-98 A1 - J.S. Byrd, PY - 1971 KW - Address counter KW - addressing logic KW - logic design KW - variable-mode counter. VL - 20 JA - IEEE Transactions on Computers ER - | |||
A design technique using complementary gating and simulated data was developed to permit a straight binary counter to be used as a variable-mode counter. Any family of binary logic modules can be used.
Index Terms:
Address counter, addressing logic, logic design, variable-mode counter.
Citation:
J.S. Byrd, "Variable-Mode Counting with Straight Binary Counters," IEEE Transactions on Computers, vol. 20, no. 1, pp. 97-98, Jan. 1971, doi:10.1109/T-C.1971.223086
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