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November 1970 (vol. 19 no. 11)
pp. 1038-1046
In this paper we present a method for obtaining a functional partitioning of the logic of a computer. It is shown that given a basic function to be performed, such as addition, the computer logic can be partitioned into four disjoint sets, namely the active information logic I, the semiactive flip-flops l, the activated control logic c, and the dormant logic D. Techniques involved in implementing the partitioning algorithm such as an event-directed simulator and three-value simulation are discussed. An application of this partitioning scheme as part of a large logic simulation system is described.
Index Terms:
Background simulation, design automation, eventdirected simulation, functional logic partitioning, simulation, threevalue value simulation.
Citation:
M.A. Breuer, "Functional Partitioning and Simulation of Digital Circuits," IEEE Transactions on Computers, vol. 19, no. 11, pp. 1038-1046, Nov. 1970, doi:10.1109/T-C.1970.222830
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