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Issue No.11 - November (1970 vol.19)
pp: 1035-1038
I.S. Reed , IEEE
ABSTRACT
This paper delineates an application of two classes of parity-check codes to the design for failure-tolerant counters. They are 1) a modified first-order Reed-Muller code and 2) the perfect Hamming code. The first code employs a majority element for implementing the error-correcting scheme while the second one makes use of a variable 2j-2+1-out-of-2j-1+1 majority element. These coding techniques can be applied in principle to other logic hardware to increase its reliability.
INDEX TERMS
Failure-tolerant counter, Hamming code, majority element, parity-check code, Reed-Muller code.
CITATION
I.S. Reed, A.C.L. Chiang, "Coding Techniques for Failure- Tolerant Counters", IEEE Transactions on Computers, vol.19, no. 11, pp. 1035-1038, November 1970, doi:10.1109/T-C.1970.222829
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