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November 1970 (vol. 19 no. 11)
pp. 1020-1028
| ASCII Text | x | ||
| G.V. Podraza, R.S. Gregg, J.R. Slager, "Efficient MSI Partitioning for a Digital Computer," IEEE Transactions on Computers, vol. 19, no. 11, pp. 1020-1028, November, 1970. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1970.222827, author = {G.V. Podraza and R.S. Gregg and J.R. Slager}, title = {Efficient MSI Partitioning for a Digital Computer}, journal ={IEEE Transactions on Computers}, volume = {19}, number = {11}, issn = {0018-9340}, year = {1970}, pages = {1020-1028}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1970.222827}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Efficient MSI Partitioning for a Digital Computer IS - 11 SN - 0018-9340 SP1020 EP1028 EPD - 1020-1028 A1 - G.V. Podraza, A1 - R.S. Gregg, A1 - J.R. Slager, PY - 1970 KW - Carry look-ahead KW - central processing unit (CPU) KW - computer architecture KW - computer partitioning KW - control state graph KW - functional building block (FBB) KW - medium-scale integration (MSI) KW - MOS technology KW - register bit slice KW - universal logic FBB. VL - 19 JA - IEEE Transactions on Computers ER - | |||
An efficient partitioning scheme based on current capability of MOS MSI technology was evolved in which four functional building blocks were defined for implementing computer digital architecture. The partitioning employs a bit slice concept to define registers and a universal logic gate for general two-or three-variable logic. A look-ahead carry for fast arithmetic and a heavily buffered OR gate structure for the control section complete the partitioning elements. Microsequencing for instruction decoding is accomplished with a state graph implemented with register FBB flip-flops.
Index Terms:
Carry look-ahead, central processing unit (CPU), computer architecture, computer partitioning, control state graph, functional building block (FBB), medium-scale integration (MSI), MOS technology, register bit slice, universal logic FBB.
Citation:
G.V. Podraza, R.S. Gregg, J.R. Slager, "Efficient MSI Partitioning for a Digital Computer," IEEE Transactions on Computers, vol. 19, no. 11, pp. 1020-1028, Nov. 1970, doi:10.1109/T-C.1970.222827
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