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Design of Asynchronous Unit Delays
October 1970 (vol. 19 no. 10)
pp. 896-902
| ASCII Text | x | ||
| V. Batra, "Design of Asynchronous Unit Delays," IEEE Transactions on Computers, vol. 19, no. 10, pp. 896-902, October, 1970. | |||
| BibTex | x | ||
| @article{ 10.1109/T-C.1970.222796, author = {V. Batra}, title = {Design of Asynchronous Unit Delays}, journal ={IEEE Transactions on Computers}, volume = {19}, number = {10}, issn = {0018-9340}, year = {1970}, pages = {896-902}, doi = {http://doi.ieeecomputersociety.org/10.1109/T-C.1970.222796}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Design of Asynchronous Unit Delays IS - 10 SN - 0018-9340 SP896 EP902 EPD - 896-902 A1 - V. Batra, PY - 1970 KW - Asynchronous KW - equivalent flow table KW - fundamental mode KW - pulse controlled. VL - 19 JA - IEEE Transactions on Computers ER - | |||
An asynchronous unit delay is an n-input n-output asynchronous sequential circuit such that the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. The delay is of significance as a building block for shift register realizations of asynchronous circuits.
Index Terms:
Asynchronous, equivalent flow table, fundamental mode, pulse controlled.
Citation:
V. Batra, "Design of Asynchronous Unit Delays," IEEE Transactions on Computers, vol. 19, no. 10, pp. 896-902, Oct. 1970, doi:10.1109/T-C.1970.222796
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