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Issue No.09 - September (1970 vol.19)
pp: 831-837
T. Janisz , IEEE
ABSTRACT
The design of present-day logic systems, using circuits with transition times approaching 1 ns, meets with problems unless the transmission lines are properly terminated. It is very inconvenient to match the input and output of a logic circuit to the characteristic impedance of a transmission line, even at the cost of considerable distortion. An alternative method is to use lines of less than 5-cm length to reduce the distortion. However, many applications require longer lines, and some applications also require interconnecting logic circuits at various points along the line. This short note considers a method of dealing with this multiple problem using frequency domain, time domain, and experimental analysis.
INDEX TERMS
Characteristic impedance, frequency domain, gateloaded line, reflections, simulated loaded line, time domain.
CITATION
T. Janisz, R.C. Martin, "Interconnection of High-Speed Logic Circuits", IEEE Transactions on Computers, vol.19, no. 9, pp. 831-837, September 1970, doi:10.1109/T-C.1970.223049
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